1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a MOSFET having an SOI (Silicon On Insulator) structure in which the threshold voltage can be controlled.
2. Description of Related Art
In order to increase the speed and integration degree of semiconductor devices, a MOSFET formed in a single crystal layer on an insulator (SOI) has been investigated. In the case where the thickness of an SOI layer is lower than the maximum depth of the depletion layer of the channel region of a MOSFET and the SOI layer is completely depleted during formation of a channel (this type of device is herein after referred to as a thin film SOIMOSFET), excellent characteristics, such as controlled short channel effect and increased effective mobility due to a moderate electric field in the direction perpendicular to the channel, in comparison with a MOSFET formed in a bulk silicon substrate, are obtained.
The MOSFET must be made to the normally-off state (the threshold voltage is positive for an N-channel) in order to apply a MOSFET to a complementary type MOS circuit. In a conventional N-channel thin film SOIMOSFET with an N.sup.+ polysilicon gate, the single crystalline layer (SOI layer) with a thickness of about 0.1 .mu.m has such a concentration of the impurity that the SOI layer is completely depleted, so that the SOI layer becomes the normally-on state, i.e., the FET is a depletion type, and it is difficult to control the threshold voltage thereof to the normally-off state or to make the FET enhancement type.
In order to make the threshold voltage to the normally-off state or the FET enhancement type, there are proposed (1) a gate electrode 130 made of a material such as P.sup.+ -polysilicon or a metal in order to utilize a difference of work function, as shown in FIG. 1 (see JP-A-01-307270), and (2) a method of providing an opposite electrode 132 on the side of the substrate 131 and applying a negative potential to the opposite electrode 132, as shown in FIG. 2 (see JP-A-02-294076).
Nevertheless, in the above (1), the range of the threshold voltage which can be controlled by the gate material is limited and the gate material must be changed when the power voltage and thus the designed threshold voltage are changed. Moreover, if a metal or silicide is used for the gate, the difference of thermal expansion coefficient with that of a silicon substrate causes a stress. In the above (2), a circuit for giving a bias voltage is required, which sacrifices the integration degree of elements.
The object of the present invention is therefore to provide a semiconductor device in which an N.sup.+ or P.sup.+ polysilicon gate is used but the threshold voltage of the thin SOIMOSFET can be easily controlled.